The present invention relates to an apparatus, such as the so-called rotary head type PCM (pulse-code modulation) tape recorder, wherein a transmission signal whose digital information is formed of a digital coded signal including synchronizing signals, for example, a pseudo video signal having a vertical synchronizing signal, a horizontal synchronizing signal and a time-sequential digital signal obtained by converting the digital information, is received through a transmission system (in this case, a recording/reproducing system, a modulating/demodulating system, etc. shall be included in the "transmission system"), and the original video digital information is detected and then used. More particularly, the invention relates to a read clock producing system for generating a read clock signal which is used for reading digital information, such as the aforementioned time-sequential digital signal in the transmission signal, from this transmission signal in synchronism therewith.
Rotary head type PCM tape recorders include one of the PCM encoder/decoder type called, e. g., "PCM audio processor", one unitarily equipped with a recording/reproducing system, etc. In any type, VTRs (video tape recorders) are applied to recording/reproducing systems in many cases. For this reason, digital information subjected to PCM is further converted into a pseudo video signal, which is inputted to or outputted from the recording/reproducing system.
In case of, e. g., the PCM audio processor, the pseudo video signal is composed of vertical synchronizing pulses, horizontal synchronizing pulses, a time-sequential digital signal portion obtained by converting the original digital information, and a white level reference signal. The digital signal portion is further divided into a data control signal, a data synchronizing signal and a data portion.
In the PCM audio processor, in decoding the original digital signal from the pseudo video signal reproduced by the VTR (in this case, a cassette type VTR for domestic use is principally utilized) which is the recording/reproducing system connected to the audio processor, data is usually derived in such a way that the digital signal portion in the pseudo video signal including the synchronizing signals and the digital signal is compared with threshold levels by comparators and is thus waveshaped, whereupon the resulting extracted signal is latched by a clock signal synchronous with the bit repetition of the data of the digital signal portion. The clock signal needs to have a frequency identical to the frequency of the time-sequential data signal. In case of generating such clock signal, it is considered to apply the phase lock by utilizing that vertical synchronizing signal of the video signal which is given as a recurrent signal. With this measure, however, a considerable difference is involved between the frequencies of the vertical synchronizing signal and the recurrent signal of the data, and the frequency division ratio of a frequency divider of PLL (phase-lock loop) for producing the required recurrence frequency of the data becomes very great. Therefore, when a jitter arises within one vertical synchronizing period, a phase lag develops between the vertical synchronizing signal and the frequency-divided signal at each time of the frequency division in correspondence with the delay of the frequency divider which is, e. g., a flip-flop or a counter. Accordingly, the phase deviation is involved in the relationship of synchronism between the data of the pseudo video signal and the clock signal obtained from the vertical synchronizing signal by dividing the frequency of the vertical synchronizing signal, and the data cannot be correctly latched.
Therefore, it has heretofore been attempted to solve the problem by, for example, applying the phase lock with the horizontal synchronizing signal.
In case of applying the phase lock with the horizontal synchronizing signal, however, an arrangement for preventing the influences of erroneous detection, noise etc. and an arrangement for processing a vertical synchronizing signal portion need to be disposed for the reasons that the horizontal synchronizing signal is more difficult of detection than the vertical synchronizing signal and is liable to incur the influences of the erroneous detection, noise etc. and that the vertical synchronizing signal portion etc. come to require special processing. This system accordingly brings about the problems that a complicated circuit arrangement is necessitated and that a stable operation is not readily attained.
In order to cope with the problems stated above, the inventor has previously proposed as Japanese patent application No. 57-104981 a system which can produce a read clock signal properly synchronized with data even by the phase lock utilizing the vertical synchronizing signal.
In this system, a signal at a frequency integral times that of the read clock signal as required by the phase lock loop is obtained on the basis of a synchronizing signal from a transmission signal which is a digital coded signal including the synchronizing signal as received through a transmission system, and it has its frequency divided into the frequency of the read clock signal by a frequency division counter. In addition, at the point of time when the leading edge of a digital information portion succeeding the synchronizing signal has been detected, the frequency division counter is reset to adjust the phase of the read clock signal to that of the digital information portion. The output of the frequency division counter is used as the read clock signal. The detection of the leading edge of the digital information portion for the resetting can, concretely, be effected in such a way that the slope of the first rise or fall of the digital information signal succeeding the synchronizing signal is compared with a predetermined threshold level.
In this case, the adjustment of the threshold level makes it possible to adjust the timing of the resetting of the frequency division counter and to adjust the phase relationship between the digital information signal and the read clock signal. Thus, the system produces the read clock signal of optimum timing, namely, the read clock signal whose rise or fall lies substantially centrally of the data bit of the digital information signal.
With such system, however, notwithstanding that the optimum value of the threshold level ought to change in response to the change of an operating point due to variations with time or to the great change of the speed of the transmission signal, the set value of the threshold level is held fixed after the adjustment, so that the read clock signal of the optimum timing fails to be produced in some cases.